The print version of SBAC-PAD 2007 program is available here to download. It compreends the program of the SBAC 2007 itself, all the workshops and marathon programming. It has a map of the conference rooms in the Serra Azul hotel and the wireless LAN and password to access the web with no charge during the event.
DAYS • Wednesday • Thursday • Friday • Saturday |
WEDNESDAY, October 24, 2007 | |
07:30 10:30 | SBAC-PAD Registration To register please provide the SBC or IEEE member card and an identification. |
10:30 10:45 | Morning Break |
10:45 12:30 | SBAC-PAD Registration To register please provide the SBC or IEEE member card and an identification. |
12:30 13:30 | Lunch |
13:30 15:10 | Session 1 - Applications I Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data Distributions by Claudio Schepke and Nicolas Maillard (Universidade Federal do Rio Grande do Sul, Brazil) Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures by Jairo Panetta, Paulo R. P. de Souza Filho, Carlos A. da Cunha Filho, Fernando M. Roxo da Motta, Silvio S. Pinheiro, Ivan Pedrosa Junior, Andre L. R. Rosa, Luiz R. Monnerat, Leandro T. Carneiro and Carlos H. B. de Albrecht (Petróleo Brasileiro SA, Brazil) Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA) by Gustavo Poli (Universidade Federal de Sao Carlos, Brazil) and Alexandre L. M. Levada (Universidade de São Paulo, Brasil) and João F. Mari, José Hiroki Saito (Universidade Federal de Sao Carlos, Brazil) Exploring Novel Parallelization Technologies for 3-D Imaging Applications by Diego Rivera, Dana Schaa, Micha Moffie and David Kaeli (Northeastern University, USA) |
15:10 16:50 | Session 2 - Microarchitecture Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor by Emre Özer, Alastair Reid and Stuart Biles (ARM Ltd., UK) Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units by Elias Mizan, Tileli Amimeur and Margarida F. Jacome (University of Texas at Austin, USA) Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications by Mafijul Md. Islam (Chalmers University of Technology, Sweden) Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors by Rafael Ubal, Julio Sahuquillo, Salvador Petit and Pedro López (Universidad Politécnica de Valencia, Spain) |
16:50 17:05 | Afternoon Break |
17:05 18:05 | Keynote Speaker 1 Luiz André Barroso Google Inc., USA The Datacenter as a Computer |
18:05 20:00 | Opening Session |
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