Invited Talks

Computer Architecture & Technology: The Road Ahead
Michael J. Flynn, Universisy of Stanford, USA

Abstract: Continuing progress in the scaling of the Silicon technology enables continuing product evolution. But in addition to simple extension of current products, several shifts in design emphasis are occurring. In the first shift more emphasis is placed on lowering power trading off increased performance. Power can be reduced by upwards to a factor of one million times from current power levels. In a second shift increased circuit density enables entire systems (computer plus memory and communications support) to be integrated on a chip.

These shifts may enable wearable (watch type) and other novel system oriented devices. As chip costs fall interconnections dominate cost and wireless/optical interconnections become all the more important.

Biography: Michael Flynn received his Ph.D. from Purdue University in 1961. He joined IBM in 1955 and for ten years worked in the areas of computer organization and design. He was design manager of prototype versions of the IBM 7090 and 7094/II, and later for the System 360 Model 91 Central Processing Unit. Between 1966 and 1974 Prof. Flynn was a faculty member of Northwestern University and the Johns Hopkins University. In 1975 he became Professor of Electrical Engineering at Stanford University, and was Director of the Computer Systems Laboratory from 1977 to 1983. He was founding chairman of both the ACM Special Interest Group on Computer Architecture and the IEEE Computer Society's Technical Committee on Computer Architecture. Prof. Flynn was the 1992 recipient of the ACM/IEEE Eckert-Mauchley Award for his technical contributions to computer and digital systems architecture. He was the 1995 recipient of the IEEE-CS Harry Goode Memorial Award in recognition of his outstanding contribution to the design and classification of computer architecture. In 1998 he received the Tesla Medal from the International Tesla Society (Belgrade), and an honorary Doctor of Science from Trinity College (University of Dublin), Ireland. He is the author of three books and over 250 technical papers.

From Superscalar and Multiprocessor to Massively Multithreading
Mario D. Nemirovsky, Kayamba, Inc.

Abstract: Microprocessor architecture has evolved significantly since the introduction of processors in the early 1970's. One line of research focused on exploiting a single thread by issuing more than one instruction per cycle. Current superscalar microprocessors are capable of issuing more than six instructions per cycle, but the Instruction Level Parallelism of a single thread, which is well below this number, limits their performance. Different techniques, including out of order execution, branch prediction, and predicative execution are used to increase the ILP within a single thread.

Multiprocessor architectures are a very efficient way to obtain high performance for independent threads, but the efficiency of MP decreases as inter-thread dependency increases. Multithreading Architectures provide an alternative approach whose origins can be traced to the CDC6600 in the 60's. These architectures increase the ILP by also exploiting thread parallelism. In the early 80's the Denelcor introduced HEP, a fine-grain multithreading supercomputer capable of tolerating memory latency, and even functional unit latency. Six systems were delivered to customers during the years 1981-1985. In the late 80's Delco Electronics developed TIO, a multithreading real-time microprocessor. This processor is still used in GM cars. In the early 90's Dynamic Multithreading (Simultaneous Multithreading - SMT) was proposed. By early 2000, both Compaq and XStream Logic announced their SMT processors and more recently, SUN, IBM and Intel also disclosed their own SMT architectures. These architectures are good to cover small latencies, however, they fall short from obtaining the high performance that can potentially be achieved for heavily parallel workloads. Last month, Kayamba introduced a new Massively Multi-Threading architecture capable of sustaining an IPC well over 32 instruction per cycle. In this talk I will briefly review these architectures, and discuss the benefit of the MMT technology.

Biography: Mario Nemirovsky has done research in many areas of computer architecture, including simultaneous multithreading, branch prediction, superscalar architecture and real-time processors. He is presently the founder CEO/CTO of Kayamba Inc. Developing a new Massively Multithreading architecture. Previously, he was the founding CEO of XstreamLogic and was the chief architect of their very high performance network processor which combines SMT, special I/O instructions, and a special register structure. Before that, he was a chief architect at National Semiconductor and at Weitek. He was one of the first to understand the power of multithreading which he termed dynamic multistreaming and first published on this subject in Micro-24 in 1991. He subsequently published results on SMT in HICSS (in 1993 and 1994) and in PACT (in 1995). This remains a core research interest of his. Mario received his PhD in ECE from UC Santa Barbara in 1990 and has been an Adjunct Professor there since 1991. Since 1998, he has also been an Adjunct Professor at UC Santa Cruz. He has produced three PhD graduates and a number of MS graduates. Two of his PhD students did their research in simultaneous multithreading. Today, Mario is an independent consultant in the field of processor implementation.

Architectural Requirements for Large Scale Internet Services
Luiz Andre Barroso, Senior Staff Engineer at Google Inc.

Abstract: Hiding behind a fairly simple web user interface lies a formidable collection of systems, technologies, and infrastructure that enables Google to serve more than two hundred million user queries per day from an index of over four billion documents. Achieving such scale while constantly improving the quality of our service is a significant challenge, and requires expertise from virtually every discipline of Computer Science. In this talk I will outline the software and hardware architecture that has enabled Google to meet such a challenge.

I will focus on how recent trends in CPU design have run contrary to the requirements of most internet service infrastructures, and describe the most important architectural features for a cost-effective clustered architecture.

Biography: Dr. Luiz Andre Barroso is a Senior Staff Engineer at Google Inc., where he focuses on improving the efficiency and robustness of Google's Web search service. His work has included cluster load balancing, fault detection and recovery, RPC-level networking infrastructure, server performance optimization, and the design of Google's hardware platform. Before joining Google, he was a Senior Member of the Research Staff at Compaq and Digital Equipment Corporations, where his group's work on processor and memory system architectures for database and web server workloads has influenced the design of commercial servers within Compaq and across the industry. While at Compaq he also co-architected and designed the Piranha system, a scalable shared memory multiprocessor based on single-chip multiprocessing. He holds B.S. and M.Sc. degrees in Electrical Engineering from PUC University, Rio de Janeiro, as well as M.S. and Ph.D. degrees in Computer Engineering from USC, Los Angeles.

Current Trends in SMP Design
Pratap Pattnaik, Senior Manager, Scalable Systems Group, IBM Research Division

Abstract: In recent years the advancements in the semiconductor technologies and the development of a highly data centric society has significantly impacted the design of the high end servers. This talk will describe the major driving forces and design points for our high end Servers. It will also highlight the major challenges and the areas of research needed to keep current high effectiveness of Servers.

Biography: Dr. Pratap Pattnaik is currently senior manager of the Scalable Systems group in IBM Research. Over the past ten years, he and his team have developed a number of key technologies for IBM's high-end eServers. His research work includes the development and design of computer systems, including both hardware and operating systems. He has also worked in the fields of parallel algorithms for molecular dynamics, solutions of linear systems, communication subsystems, fault management subsystems, quantum Monte Carlo and high-temperature superconductivity. He has over ten years of research experience in various aspects of integrated circuit design and fabrication, silicon processing, and condensed matter theory. Dr. Pattnaik received a Ph.D. in Physics from the Massachusetts Institute of Technology in 1980.