Keynote Talks

"HPC Clouds: Raining Multicore Services", Dan Reed (Microsoft Research)

"The 1000 core microprocessor: Will we be ready for it?", Yale Patt (University of Texas at Austin)

"GPUs in High-Performance Computing architectures, software stack, education, and applications", Wen-Mei Hwu (University of Illinois at Urbana-Champaign)

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 ABSTRACT

Scientific and technical computing are at an inflection point, where system scale, complexity and operating costs, together with the explosive growth of data and the availability of high-speed networks, are changing the ways we will deliver technical computing services. Scientific discovery, business practice and social interactions are moving rapidly from a world of homogeneous and local systems to a world of distributed software, virtual organizations and cloud computing infrastructure, supported by ever larger computing infrastructure. Where is the technology going and what are the research implications? What architectures and policies are appropriate for different user bases? How do we build scalable infrastructure and what is the role of government, academia and industry? How do we develop and support software? What is the ecosystem of components in which they will operate? How do we optimize performance, power and reliability?

 SPEAKER BIOGRAPHY

Daniel A. Reed is Microsoft's Corporate Vice President for the Extreme Computing Group, responsible for R&D on parallel and extreme scale computing, including cloud infrastructure. Previously, he was the Chancellors Eminent Professor at UNC Chapel Hill, as well as the Director of the Renaissance Computing Institute (RENCI) and the Chancellors Senior Advisor for Strategy and Innovation for UNC Chapel Hill. Dr. Reed has served as a member of the U.S. Presidents Council of Advisors on Science and Technology (PCAST) and as a member of the Presidents Information Technology Advisory Committee (PITAC). He recently chaired a review of the U.S. networking and IT research portfolio and completed two terms as chair of the board of directors of the Computing Research Association (CRA).

He was previously Head of the Department of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He has also been Director of the National Center for Supercomputing Applications (NCSA) at UIUC, where he also led National Computational Science Alliance. He was also one of the principal investigators and chief architect for the NSF TeraGrid. He received his PhD in computer science in 1983 from Purdue University.

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 ABSTRACT

Process technology predicts 50 billion transistors on a chip in the next six or eight years, and there are plenty of existence proofs of single-core microprocessors with around 50 million transistors. Simple mindless arithmetic yields a 1000 processor chip. But because we will be able to produce a chip with 1000 cores does not mean we should produce one. And, if we do, will be able to harness it effectively? I would like to do two things in this talk today: first, review the history that brought us to our current state of multi-core chips, and ask if there isn't a better way, moving forward. A comment like "Today, Moore's Law is about doubling the number of cores on the chip" is one example, in my view, of continuing the current nonsense. Second, I would like to focus on some fundamental problems we will face when the number of transistors permits a 1000 core chip: algorithm development in a domain where the costs of communication and processing are totally different than they are today, off-chip (and on-chip) bandwidth, power considerations, which can involve much more than simply running the clock more slowly. And, as is usually the case, at the heart of whether or not we will be ready is education.

 SPEAKER BIOGRAPHY

Yale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin.

Today, Yale Patt works on problems for the microprocessors of the year 2015, when technology promises each chip will contain more than ten billion transistors. Some of his current activities include Subordinate Simultaneous Microthreading (aka helper threads), a variation of Simultaneous Multithreading that is particularly useful in sequential threads of control, cluster processing, the Block-structured ISA, Selective V-way caches, Run-ahead execution, and Wish branches.

Yale Patt earned his BS at Northeastern University and his MS and PhD at Stanford University, all in electrical engineering. He received the 1995 IEEE Emannuel R. Piore Medal "for contributions to computer architecture leading to commercially viable high performance microprocessors," the 1996 IEEE/ACM Eckert-Mauchly Award "for important contributions to instruction level paralelism and superscalar processor design," and the 1999 IEEE Wallace W. McDowell Award "for your impact on the high performance microprocessor industry via a combination of important contributions to both engineering and education." In 2005, he received the IEEE Computer Society Charles Babbage Award "for fundamental contributions to high performance processor design." He is a Fellow of both the IEEE and the ACM.

For his teaching, he has received several awards, most notably the ACM Karl V. Karlstrom Outstanding Educator Award for 2000. He also received the 2002 Texas Excellence Teaching Award for the College of Engineering at The University of Texas at Austin. Also, the 2002 Dad's Centennial Fellowship for his commitment to teaching freshmen. At Michigan, he was named Outstanding Professor of the Year by the Michigan Chapter of Eta Kappa Nu in 1992. He received the Teaching Excellence Award of the EECS Department at Michigan in 1995 and the College of Engineering of Michigan in 1996. In 1998, he was named an Arthur F. Thurnau professor at Michigan for his commitment to undergraduate education. In 1999 (for the academic year 1998-1999), and again in 2001 (for the academic year 2000-2001), he was named the National ACM Lectureship Program's Outstanding Lecturer of the Year.

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 ABSTRACT

Modern GPUs such as the NVIDIA GTX280 series are massively parallel, many-core compute engines. According to the semiconductor industry scaling roadmap, these compute engines could scale up to 10,000x the peak performance of a circa-2007 microprocessor core by the end of the year 2016. Such a dramatic increase in computation power will likely trigger multiple major science discoveries as well as revolutions in consumer applications. We are experiencing a once-in-a-life-time opportunity in our profession. However, the programming and code optimization models of GPU computing are quite different from those of parallel systems based on traditional CPUS. In this presentation, I will describe the recent progress by the HPC community in building GPU-based clusters, enhanced software stacks, educational materials , and porting applications to fully exploit the current and future GPU computing platforms. I will then discuss the coming challenges and some promising work to address these challenges.

 SPEAKER BIOGRAPHY

Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His research interests are in the area of architecture, implementation, and software for high performance computer systems. He is the director of the IMPACT research group . For his contributions in research and teaching, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and ISCA Most Influential Paper Award. He is a fellow of IEEE and ACM. He leads the GSRC Concurrent Systems Theme. He co-directs the new $18M UIUC Intel/Microsoft Universal Parallel Computing Research Center with Marc Snir and serves as one of the principal investigators of the $208M NSF Blue Waters Petascale computer project. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.