Parallelism: A serious goal or a silly mantra

Speaker: Prof. Yale Patt – U. of Texas at Austin and the Ernest Cockrell, Jr. Centennial Chair in Engineering

The popular mantra these days is "Paralelismo acima de tudo," undoubtedly in large part due to the highly visible and well advertised continuing benefits of Moore's Law, manifest as more and more cores on a chip.

More cores = more opportunity for parallelism. Whether we can effectively utilize them or not does not seem to matter. We also get such silliness as advice to break the problem in half and run the two halves concurrently, thereby saving half the energy, unmindful of whether the problem can be broken in a way that allows the two halves to run concurrently. Or, hardware is sequential, thereby confusing what it is about hardware that is sequential and what it is that is parallel. Or, thinking in parallel is hard. In this talk, I would like to examine some of the fundamentals, and see what it will take to exploit the obvious opportunity of chips with a thousand processors.

I will start with the single overarching mechanism needed to enable parallelism, how that mechanism has played out in the parallelism present in single core uniprocessor chips, and where we might use it effectively moving forward. Along the way we will examine some notions that, if properly observed, could become features instead of bugs: dark silicon, Amdahl's Law, the future of ILP, for example. Most importantly, we need to understand who needs to be involved if we are really going to exploit parallelism in tomorrow's computers.

Short Biography

Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, directing the research of eight PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students.

The textbook for his unconventional approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Jeram Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide. He has received the highest honors in his field for both his reasearch (the 1996 IEEE/ACM Eckert-Mauchly Award) and teaching (the 2000 ACM Karl V. Karlstrom Outstanding Educator Award). He was the inaugural recipient of the newly established IEEE Computer Society Bob Rau Award in 2011, and was recently named the 2013 recipient of the IEEE Harry Goode Award. He is a Fellow of both IEEE and ACM. More detail can be found on his web page

The challenge of Fault-Tolerance mechanisms for power-efficient massive parallel systems

Speaker: Prof. Avi Mendelson – CS/EE Technion Haifa Israel

It is expected that soon, hundreds or even thousands of cores will be integrated on a single chip. Thus, large scale systems, such as cloud computers or HPC systems will be built out of millions of cores, sophisticated communication and vast memory subsystems. In such systems, faults cannot be avoided, but the system needs to be built to handle them in the most efficient way.

The talk will present different hardware based and software based mechanisms that were proposed to handle faults in massive parallel systems. Then, it will focus on a new “software-hardware” interfaces we developed as part of the “Teraflux” project sponsored by the EU as part of the FP7 research framework.

Short Biography

Avi Mendelson is a professor in the CS and EE departments Technion, Israel, and a member of the TCE (Technion Computer Engineering center). He earn his BSC and MSC degrees from the CS department, Technion, and got his PhD from University of Massachusetts at Amherst (UMASS).

Prof. Avi Mendelson has a blend of industrial and academic experience. As part of his industrial role, he spent 11 years in Intel, where he served as a senior researcher and Principle engineer in the Mobile Computer Architecture Group, in Haifa. While in Intel he was the chief architect of the CMP (multi-core-on-chip) feature of the first dual core processors Intel developed.

His research interests span over different areas such as Computer architecture, Operating systems, Power management, reliability, fault-tolerance, cloud computing, HPC and GPGPU.

Recently he served as the general manager of the ISCA-40 conference that was held in Tel-Aviv.

Killer-mobiles: the way towards energy efficient High Performance Computers?

Speaker: Prof. Mateo Valero – Universitat Politècnica de Catalunya

It is widely recognized that Exascale systems will be constrained by power. The Mont-Blanc project aims to build an alternative approach towards Exascale based on aggregating parts from the embedded and mobile market, which offer a better FLOPS/Watt ratio and a lower unit cost, at the expense of lower peak performance per chip. HPC systems built from these parts will require a higher number of processors, or resort to extensive use of compute accelerators. Using a higher number of chips increases the available memory bandwidth, alleviating the bandwidth wall, but increases the pressure on the interconnection network.

The use of a high number of processors and accelerators, and the increased pressure on the interconnect require extensive code optimizations to achieve strong scaling, point to point synchronizations, and overlap data transfer with computation. The role of the OmpSs parallel programming model is paramount, as the key enabling technology that hides the complexity from the programmer, and transparently performs all the required optimizations.

In this talk, we will review the design philosophies of several vendors, including HPC compute accelerators, and ARM-based mobile application processors in terms of peak performance, memory bandwidth, and energy efficiency; and we will review how the OmpSs programming models exploits the benefits of the Mont-Blanc approach while overcoming the drawbacks

Short Biography

Mateo Valero , is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 600 papers, has served in the organization of more than 300 International Conferences and he has given more than 400 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award, Harry Goode Award, ACM Distinguished service, the “King Jaime I” in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria, Zaragoza and Complutense de Madrid in Spain and by the University of Veracruz in Mexico. "Hall of the Fame" member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008)

In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science, in 2006 member of the Royal Spanish Academy of Doctors, in 2008 member of the Academia Europaea and in 2012 Correspondant Academic of the Mexican Academy of Sciences. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow.

(*): Unfortunately, due to an unexpected situation, the talk of Prof. Ian Foster has been cancelled

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