Technical Program:
Oct 18th - 9:00 - 10:00 - Session
1 - High Performance Applications
ParTriCluster: A Scalable Parallel Algorithm
for Gene Expression Analysis
Renata Araujo, Guilherme
Trielli, Gustavo Orair, Wagner Meira Jr., Renato Ferreira, and Dorgival Guedes
Towards Production Code Effective Portability
among Vector Machines and Microprocessor-Based Architectures
Alvaro L. Fazenda,
Eduardo H. Enari, Luiz F. Rodrigues, and Jairo Panetta
Oct 18th - 10:30 - 12:00 - Session
2 - Grid and Cluster Computing 1
Data Segmentation Management Infrastructure in
a Database Grid
Reinaldo L. and Sergio T. Kofuji
Detecting Malicious Manipulation in Grid
Environments
Felipe Martins, Marcio
Maia, Rossana M. de Castro Andrade, Aldri L. dos Santos, and Jose N. de Souza
Policy-Based Resource Allocation in
Hierarchical Virtual Organizations for Global Grids
Kyong Hoon Kim and Rajkumar Buyya
Oct 18th - 14:00 - 15:00 -
Keynote Speech - Joel Saltz
Oct 18th - 15:00 - 16:30 - Session
3 - Processor Microarchitecture
A Speculative Trace Reuse Architecture with
Reduced Hardware Requirements
Mauricio L. Pilla, Bruce
R. Childers, Amarildo T. da Costa, Felipe M. G. Franca, and Philippe O. A. Navaux
Controlling the Power and Area of Neural Branch
Predictors for Practical Implementation in High-Performance Processors
Daniel A. Jimenez and Gabriel H. Loh
The mDTSVLIW: A Multi-Threaded Trace-based VLIW
Architecture
Peter Rounce and Alberto F. De Souza
Oct 18th - 17:00 - 18:00 - Session 4 - Grid and Cluster Computing 2
GerpavGrid: Using the Grid to Maintain the City
Road System
Cesar A. F. De Rose, Tiago
C. Ferreto, Marcelo B. de Farias, Vladimir G. Dias, Walfredo Cirne, Milena P.
M. Oliveira, and Katia Saikoski
A Run-Time System for Efficient Execution of
Scientific Workflows on Distributed Environments
George Teodoro, Tulio Tavares, Renato Ferreira,
Tahsin Kurc, Wagner Meira Jr., Dorgival Guedes, Tony Pan, and Joel Saltz
Oct 19th - 8:30 - 10:00 - Session 5 - Performance Measurement and Analysis
Dual-Thread Speculation: Two Threads in the
Machine are Worth Eight in the Bush
Fredrik Warg and Per Stenstrom
Characterizing the Performance of Data
Management Systems on Hyper-Threaded Architectures
Wessam M. Hassanein, Moustafa A. Hammad, and
Layali Rashid
Ultra-Fast CPU Performance Prediction:
Extending the Monte Carlo Approach
Ram Srinivasan, Jeanine Cook, and Olaf Lubeck
Oct 19th - 10:30 - 12:30 - Session
6 - Memory Hierarchy Architecture
Scalable Value-Cache Based Compression Schemes
for Multiprocessors
Martin Thuresson and Per Stenstrom
Tuning Mechanism for Two-Level Cache Hierarchy
Intended for Instruction Caches and Low Energy Consumption
Abel G. Silva Filho,
Pablo Viana, Edna Barros, and Manoel E. Lima
Applying the Zeros Switch-Off Technique to Reduce Static Energy in Data Caches
Rafael Ubal, Julio Sahuquillo, Salvador Petit,
and Pedro Lopez
32-Core CMP with Multi-Sliced L2: 2 and 4 Cores
Sharing a L2 Slice
Mario D. Marino
Oct 19th - 14:00 - 15:00 -
Keynote Speech - Kazuaki Murakami
Oct 19th - 15:00 - 16:30 - Session
7 - Parallel and Distributed Algorithms, Architectures and Interconnection Networks
Scalable Parallel Implementation of Bayesian
Network to Junction Tree Conversion for Exact Inference
Vasanth Krishna Namasivayam, Animesh Pathak,
and Viktor K. Prasanna
Combining Source Routing and Dynamic Fault
Tolerance
Frank O. Sem-Jacobsen, Olav Lysne, and Tor
Skeie
Runtime System Support for Running Applications
with Dynamic and Asynchronous Task Parallelism in Software DSM Systems
Rafael Mendes, Lauro Whately, Maria Clicia de
Castro, Cristiana Bentes, and Claudio L. Amorim
Oct 20th - 9:00 - 10:00 - Session
8 - Reconfigurable Systems and Operating System
Support for Specific Applications
Reconfigurable System with Virtuoso Real-Time
Kernel and TEV Environment
Mairum C. Andrade, Celio
E. Moron, and Jose H. Saito
Virtual-Machine-Based Intrusion Detection on
File-Aware Block Level Storage
Youhui Zhang, Yu Gu, Hongyi Wang, and
Dongsheng Wang
Oct 20th - 10:30 - 11:30 -
Keynote Speech - Margaret Martonosi
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