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Campo Grande/MS, February 10th, 2009
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Conference Overall Schedule

Day 1
October 29, 2008

Day 2
October 30, 2008

Day 3
October 31, 2008

Day 4
November 1, 2008

Day 3 – Friday – October 31, 2008

Room Paiaguás

Room Taquari

Room Bodoquena

Room Nabileque




SBAC Session 6


Sessão 5







Keynote 2






SBAC Session 7

Minicurso 1





 Keynote 3





Tutorial 2

Minicurso 2




SBAC Meeting



SBAC Session 6 – Grid, Cluster, and Operating System
Day 3 - Friday - October 31 – 08:00 – 08:30 – Room Paiguás

  • Measuring Operating System Overhead on CMT Processors by Petar Radojkovic, Vladimir Cakarevic, Francisco Cazorla, Roberto Gioiosa (BSC- Barcelona Supercomputing Center - Spain) and Alejandro Pajuelo and Javier Verdu (Polytechnic University of Catalonia - Spain)
  • Aspect-based patterns for grid programming by Luis Daniel Benavides Navarro, Remi Douence, Fabien Hermenier, Jean-Marc Menaud and Mario Sudholt (Ecole des Mines de Nantes - France)
  • A Reconfigurable Run-Time System for Filter-Stream Applications by Daniel Fireman, George Teodoro, André Souza and  Renato Ferreira (Federal University of Minas Gerais - Brazil)

SBAC Session 7 – Memory Systems
Day 3 - Friday - October 31 – 13:00 – 15:00 – Room Paiguás

  • Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-core Co-design by James Poe, Chang-Burm Cho and Tao Li (University of Florida - USA)
  • Performance Sensitivity of NUCA Caches to On-Chip Network Parameters by Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli and Cosimo Prete (University of Pisa - Italy)
  • A Software Transactional Memory System for an Asymmetric Processor Architecture by Felipe Goldstein, Alexandro Baldassin, Rodolfo Azevedo, Paulo Centoducatte (State University of Campinas - Brazil) and Leonardo Garcia (IBM - Brazil)
  • Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations by Leandro Marzulo, Felipe França and  Vitor Costa (Federal University of Rio de Janeiro – Brazil)

SBAC Keynote 2 - Trevor Mudge, Bredt Family Professor of Engineering The University of Michigan, Ann Arbor
Day 3 - Friday - October 31 – 10:00 – 11:00 – Room Paiguás

Title: PicoServer - Building a Compact Energy Efficient Multiprocessor
Abstract: With power and cooling becoming an increasingly costly part of the operating budget of a server, the old trend of striving for higher performance with little regard for power is over. Emerging semiconductor process technologies, multicore architectures, and new interconnect technology provide an avenue for future servers to become low power, compact, and possibly mobile. In talk we examine two techniques for achieving low power: 1)3D die stacking; and 2) replacing DRAM with Flash memory. 3D die stacking technology can bond multiple dies together vertically and provide millions of connections between layers. In this talk, we examine the case for a PicoServer, a multicore architecture using 3D stacking to implement a simple, low-power, high-performance server system. Secondly, we will show how Flash memory, a low power high density non-volatile memory technology, can be used to replace DRAM, lowering the power of the main memory, to further reduce power.
Brief Bio: Trevor Mudge received a Ph.D. in Computer Science from the University of Illinois, Urbana. Since then, he has been at the University of Michigan, Ann Arbor. He became the Bredt Family Professor of Electrical Engineering and Computer Science after a ten year term as the Director of the Advanced Computer Architecture Laboratory - a group of about 10 faculty and 80 graduate students. He has co-authored numerous papers on computer architecture, programming languages, VLSI design. He has also chaired 38 theses. Trevor Mudge is a Fellow of the IEEE, a member of the ACM, the IET, and the British Computer Society.

SBAC Keynote 3 - Jose Eduardo Moreira (IBM Research)
Day 3 - Friday - October 31 – 15:00 – 16:00 – Room Paiguás

Title: Scale-up and Scale-out: Evolution and Trends in Parallel Processing.
Abstract: An active research area since the 60s, parallel processing became mainstream in the information technology industry in the 90s. First, symmetric multiprocessors, or  scale-up systems, with increasing number of processors became popular. More recently, clusters of interconnected machines, or scale-out systems, are the backbone of new important applications such as search engines and electronic markets. In this talk, we review the evolution and characteristics of these two types of systems. We identify their strengths and weaknesses and also the pain points associated with using them. We discuss new ideas that seek to combine the best of both worlds and present some results on that front. Finally, we discuss what are the business and innovation opportunities that can lead to new kinds of systems for parallel
Brief Bio: José E. Moreira received B.S. degrees in physics and electrical engineering in 1987 and an M.S. degree in electrical engineering in 1990, all from the University of Sao Paulo, Brazil. He received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 1995. Since joining IBM in 1995, he has been involved in several high-performance computing projects, including the Teraflop-scale ASCI Blue-Pacific, ASCI White, and Blue Gene/L, for which he was the System Software Architect. Since 2006, José has been Chief Architect of the Commercial Scale Out initiative at IBM Research to develop superior scalable solutions for commercial computing. Just recently,  José started in a new project to design the next generation of AIX enterprise servers at IBM Research.

SBAC Tutorial 2 - Alfredo Goldman e Raphael Camargo
Day 3 - Fridya - October 31 – 16:00 – 19:00 – Room Paiaguás

Title: Computational Grids: Basic Concepts and Concrete Examples
Abstract: Computationally-intensive problems that require large amounts of processing power are increasingly important for advances in science and technology in a wide variety of areas such as Physics, Chemistry, Biology, Engineering, and Finance. Up to the middle of the 1990s, these problems were resolved using large and highly-expensive parallel computers accessible to few research groups. Over the last 10 years, however, it became more efficient and inexpensive to invest in assembling and configuring clusters of inexpensive, commodity personal computers. These PC clusters can offer very large processing powers at a relatively low cost. Recently, the idea of linking multiple, geographically distributed clusters for the establishment of Computational Grids have been receiving more and more attention in both academia and industry. In this chapter, we present the basic concepts behind Grid Computing and describe some of the most important grid middleware systems and the programming models they support. Finally, we give a general overview of some of the most relevant grids currently in use.
Brief Bio: Alfredo Goldman received his B.Sc. in applied mathematics from University of São Paulo, Brazil, his M.Sc. in computer science also from University of São Paulo, and his doctorate in computer science from the Institut National Polytechnique de Grenoble, France. He currently is an associated professor in the Department of Computer Science at University of São Paulo. His research interests include parallel and distributed computing, mobile computing and grid computing. Alfredo has published more than 60 papers in several journals and conferences, and is subject area editor of Parallel Computing (Elsevier). Raphael Yokoingawa de Camargo is Professor at University of São Paulo, at the School of Arts, Sciences and Humanities. He obtained his doctoral degree in Computer Science at University of Sao Paulo in 2007. Has experience in the areas of Distributed Systems, Computational Grids, Fault-tolerance and distributed data storage. Raphael has published in several important journals and conferences, such as Concurrency & Computation: Practice & Experience, IEEE Distributed Systems Online, IEEE CCGrid and SBAC-PAD.


WSCAD Sessão 5  – Arquitetura de Computadores II
Sexta-feira - 31 de Outubro – 10:00 - 11:15 – Sala Bodoquena

  • PowerSMT: Ferramenta para Análise de Consumo de Potência em Arquiteturas SMT
    Rogerio A. Goncalves (Universidade Estadual de Maringá), Ronaldo A. L. Goncalves (Universidade Estadual de Maringá)
  • PBIW: Uma Codificação de Instruções Alternativa para Arquiteturas de Alto Desempenho
    Rafael Batistella (Unicamp), Ricardo Santos (Universidade Catolica Dom Bosco), Rodolfo Azevedo (UNICAMP)
  • Uma Arquitetura para Compressão de Código em Processadores Embarcados
    André da Silva (Universidade Federal do Rio de Janeiro), Gabriel Silva (UFRJ)

WSCAD Minicurso 1: Virtualização: conceitos e aplicações em processamento paralelo - Alexandre da Silva Carissimi
Quinta-feira, 30 Outubro, 8:00 – 9:30, Sala Bodoquena
Sexta-feira, 31 Outubro, 13:00 – 14:30, Sala Bodoquena

Resumo: Virtualização é a técnica que permite particionar um único sistema computacional em vários outros denominados de máquinas virtuais. Cada máquina virtual oferece um ambiente completo muito similar a aquele oferecido por uma máquina física podendo ter seu próprio sistema operacional, bibliotecas, aplicativos e serviços de rede (protocolos Internet). Por emularem um ambiente computacional sobre outro, as máquinas virtuais impõem algumas restrições de implementação e desempenho. Entretanto, dado as vantagens que a virtualização apresenta, se observa um investimento maciço nesta tecnologia por parte dos fabricantes de hardware de software. Os processadores mais recentes da Intel e da AMD já foram concebidos prevendo suporte em hardware para a virtualização. Em relação ao software, se encontram diversos produtos e ambientes, onde pode se destacar as soluções da Microsoft,  VMware, Citrix (XenSource) e Sun Micorsystems. Esse movimento em relação a virtualização chamou a atenção dos membros da comunidade de processamento de alto desempenho (PAD). As principais áreas de interesse são o projeto e o desenvolvimento de sistemas operacionais, de ambaintes de programação e práticas de administração e gerenciamento de recursos, em especial para computação em cluster e grids. O minicurso tem por objetivo capacitar o participante a entender o que é a virtualização, suas vantagens e desvantagens e como ela pode ser explorada em uma infra-estrutura de PAD.

Alexandre da Silva Carissimi possui graduação em Engenharia Elétrica pela Universidade Federal do Rio Grande do Sul (1985), mestrado em Ciências da Computação pela Universidade Federal do Rio Grande do Sul (1989) e doutorado em Informática - Institut National Polytechnique de Grenoble (1999). Atualmente é professor 40/DE da Universidade Federal do Rio Grande do Sul, lotado no Departamento de Informática Aplicada. Tem experiência na área de Ciência da Computação, com ênfase em Software Básico, atuando principalmente nos seguintes temas: redes de computadores, sistemas operacionais, sistemas distribuídos, ambientes de programação paralela e ambientes de programação.

WSCAD Minicurso 2: Computação de alto desempenho utilizando CUDA - Rodolfo Azevedo e Bruno Lopes
Quinta-feira, 30 Outubro, 13:00 - 14:30, Sala Bodoquena
Sexta-feira, 31 Outubro, 16:30 – 18:00, Sala Bodoquena

Resumo:  As recentes arquiteturas de processamento gráfico em tempo real são em sua maioria implementações comerciais do modelo de stream processors programáveis. Este trabalho explora o funcionamento interno desta arquitetura e as linguagens de programação criadas ao longo dos anos que facilitam a criação de software, com o foco nas placas gráficas da NVIDIA série 8 e o modelo de programação \emph{CUDA}. Através deste modelo de programação e das novas placas de vídeo, é possível obter ganhos de desempenho de 1 ou 2 ordens de grandeza em relação aos processadores convencionais.

O professor Rodolfo Azevedo é doutor em Ciência da Computação pelo Instituto de Computação da Unicamp. Atualmente é professor do Instituto de Computação da UNICAMP. Já orientou 11 dissertações de mestrado e 2 teses de doutorado. Publicou artigos em grandes conferências internacionais como DAC, DATE, CASES, ISLPED, ASAP e em revistas como IEEE TVLSI, IJPP, DAES e JUCS. O Prof. Rodolfo Azevedo foi co-autor de um trabalho que recebeu o prêmio de melhor artigo do SBAC-PAD 2004. Suas áreas de interesse são Arquitetura de Computadores, Sistemas Dedicados, Compressão de Código, Baixo Consumo de Energia e Linguagens de Descrição de Arquitetura.

Bruno Cardoso Lopes atualmente cursa mestrado na Universidade Estadual de Campinas (Unicamp). Têm experiência academica em pesquisas envolvendo simulação de hardware e compressão de código. Profissionalmente já trabalhou com desenvolvimento para sistemas embarcados, com o foco em drivers para Linux e FreeBSD. É também contribuidor ativo no desenvolvimento do compilador open source LLVM (Low Level Virtual Machine, www.llvm.org), onde é atualmente maintainer do back-end MIPS.