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Campo Grande/MS, February 10th, 2009
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LAGrid 2008
WEAC 2008
WPUC 2008
Documento sem título

Conference Overall Schedule

Day 1
October 29, 2008

Day 2
October 30, 2008

Day 3
October 31, 2008

Day 4
November 1, 2008

Day 1 – Wednesday – October 29, 2008

Room Paiaguás

Room Taquari

Room Bodoquena

Room Nabileque





LAGrid 2008









Sessão 1


Session 1




Session 2

Sessão 2







Keynote 1



Opening Session



SBAC Session 1 – Architecture I
Day 1 - Wednesday - October 29 - 13:30 - 15:00 – Room Paiguás

  • Accurate and Low-Overhead Dynamic Detection and Preduction of Program Phases Using Branch Signatures by Balaji Vijayan (Intel Corporation, USA) and Dmitry Ponomarev (SUNY Binghamton, USA)
  • Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt by Jason Loew (Binghamton University) and Dmitry Ponomarev (SUNY Binghamton)
  • An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance using the NSGAII Algorithm by Abel Silva-Filho, Carmelo Bastos Filho, Davi Marinho, Filipe Cordeiro and Rodrigo Castro (Pernambuco State University - Brazil)

SBAC Session 2 – Applications I
Day 1 - Wednesday October 29 - 15:00 – 16:30 – Room Paiguás

  • On Simulated Annealing Applied on the Scheduling of Parallel Applications by Rodrigo Mello (University of São Paulo - Brazil) and Luciano José Senger (State University of Ponta Grossa - Brazil)
  • Controlling Processes Reassignment in BSP Applications by Rodrigo Righi, Laércio Pilla, Alexandre Carissimi and Philippe Navaux (Federal University of Rio Grande do Sul - Brazil)
  • A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation by Thiago Farias, Mozart Almeida, Marcelo Teixeira, Veronica Teichrieb  and  Judith Kelner  (Federal University of Pernambuco- Brazil)

SBAC Keynote 1 - Chatterjee Siddhartha, Director, IBM Austin Research Laboratory, IBM Research Division
Day 1 - Wednesday October 29 - 17:00 – 18:00 – Room Paiguás

Title: Parallel Programming and Speculative Execution.
Abstract: Transactional Memory (TM) and Thread Level Speculation (TLS) are examples of programming paradigms supported across the system that are targeted toward enabling multi-core exploitation. Using a workload driven approach we evaluate these techniques from two perspectives: the amount of parallelism exposed by using speculative programming paradigms and the effectiveness of different systems to exploit such parallelism. We discuss the performance and parallelism models, present tools that we used to evaluate our workloads against these models. We also present an overview of our work on the freely available IBM Software Transactional Memory system and detailed results on the runtime and compiler issues for STM.
Brief Bio: Dr. Siddhartha Chatterjee is director of the Austin Research Laboratory, one of IBM’s eight worldwide research laboratories. He also serves as the Research area strategist for systems architecture.  He has held technical, managerial, executive, strategy, and staff positions during his time in the IBM Research Division.  Most recently, he was senior manager of the Systems Solutions and Architecture group at IBM Thomas J. Watson Research Center, Yorktown Heights, NY.  Earlier, he was the leader of the Blue Gene performance team. Dr. Chatterjee received his B.Tech. in electronics and electrical communications engineering in 1985 from the Indian Institute of Technology, Kharagpur, and his Ph.D. in computer science in 1991 from Carnegie Mellon University.  Before joining IBM Research, he was a visiting scientist at the Research Institute for Advanced Computer Science (RIACS) in Mountain View, California, from 1991 through 1994, and was assistant and associate professor of computer science at the University of North Carolina at Chapel Hill from 1994 through 2001.  He is currently an adjunct professor of computer science at the University of Texas at Austin. Dr. Chatterjee has performed research and published in the areas of compilers for parallel languages, computer architecture, and parallel algorithms.  His research interests include the design and implementation of programming languages and systems for high-performance applications, memory hierarchy issues in high-performance systems, and software quality.  He is an ACM Distinguished Scientist, an IEEE Senior Member, and a Sigma Xi member.

WSCAD Sessão 1 – Algoritmos Paralelos e Distribuídos
Quarta-feira - 29 de Outubro - 13:00 - 15:05 – Sala Taquari

  • Paralelização de Metaheurísticas para Execução Autonômica em Grades Computacionais
    Aletéia Araújo (Universidade Católica de Brasília), Cristina Boeres (UFF), Vinod Rebello (UFF) e Celso Ribeiro (UFF)
  • Algoritmos Distribuídos para Roteamento em Redes Tolerantes a Atrasos e Desconexões
    Anna Dolejsi (Universidade Federal Fluminense), Gabriel Argolo (UFF), Lúcia Drummond (Universidade Federal Fluminense), Melba Gorza (UFF)
  • Um Compressor de Arquivos Paralelo Compatível com o Bzip2
    Vinícius Dalto do Nascimento (UFRJ), Davi Garcia (Universidade Federal do Rio de Janeiro), Gabriel Silva (UFRJ)
  • Método SOR Paralelo na Simulação das Equações de Navier-Stokes 2D
    Guilherme Galante (Universidade Estadual do Oeste do Paraná), Rogério Rizzi (Universidade Estadual do Oeste do Paraná), Darlon Vasata (UNIOESTE)
  • Métodos Multigrid Paralelos em Malhas Não Estruturadas Aplicados à Simulação de Problemas de Dinâmica de Fluidos Computacional e Transferência de Calor
    Guilherme Galante (Universidade Estadual do Oeste do Paraná), Rogério Rizzi (Universidade Estadual do Oeste do Paraná)

WSCAD Sessão 2 – Arquitetura de Computadores I
Quarta-feira - 29 de Outubro – 15:15 - 16:30 – Sala Taquari

  • IPNoSys: uma nova arquitetura paralela baseada em redes em chip
    Silvio Fernandes (UFRN), Bruno Cruz de Oliveira (Universidade Federal do Rio Grande do Norte), Miklécio Costa (Universidade Federal do Rio Grande do Norte), Ivan Silva (Universidade Federal do Rio Grande do Norte)
  • DTSD: Uma Arquitetura com Mecanismo Híbrido de Execução
    Fernando Almeida (Universidade Federal do Espírito Santo), Alberto De Souza (Universidade Federal do Espírito Santo), Edil Fernandes (COPPE-UFRJ)
  • FlowPGA: DataFlow de Aplicações em FPGA
    Leandro Marzulo (COPPE/UFRJ), Fabio Flesch (COPPE UFRJ), Alexandre Nery (COPPE UFRJ), Felipe França (COPPE-UFRJ), Edil Fernandes (COPPE-UFRJ)