Program
| Wednesday, October 27, 2004 - Day 1 | |
| 07:30 |
Conference Registration
|
| 08:00 09:30 |
Tutorial 1 (Part 1):
Just-in-Time
HW/ISA/SW Co-optimization Techniques for SoC |
| 09:30 |
Coffee Break
|
| 09:45 11:25 |
Session 1:
Cache and Memory Architectures
Cache Filtering Techniques to
Reduce the Negative Impact of Useless Speculative Memory
References on Processor Performance
Self-Monitored Adaptive Cache
Warm Up for Microprocessor Simulation
The eDRAM based
L3-Cache of the BlueGene/L Supercomputer Processor Node
Multi-Profile
Instruction Based Compression
|
| 11:25 12:25 |
Invited Talk 1:
The Role of
Virtual Machines in Future Computer Systems
|
| 12:25 |
Lunch
|
| 13:45 15:00 |
Session 2:
Processor Architectures I A Study of
Errant Pipeline Flushes caused by Value Misspeculation
Design Space
Exploration using T&D-Bench
Value Predictors
for Reuse through Speculation on Traces
|
| 15:00 16:00 |
Invited Talk 2:
The Gridbus Toolkit for Building and Deploying eScience
Applications on Utility Grids
|
| 16:00 |
Coffee Break
|
| 16:15 17:30 |
Session
3: Processor Architectures II IATO: A Flexible
EPIC Simulation Environment
ArchC: A
SystemC-Based Architecture Description Language
Optimizations
for compiled simulation using instruction type information
|
| 17:30 19:00 |
Tutorial 1 (Part 2):
Just-in-Time
HW/ISA/SW Co-optimization Techniques for SoC
|
| 19:00 20:30 |
Panel
Computing
Challenges: what will influence progress (for better or
worse)
|